Field of Invention
The present invention is related to an integrated circuit and a method of forming the same, and more particularly to a semiconductor device and a method of forming the same.
Description of Related Art
As technology advances, the semiconductor device is minimized to meet the trend of lighter, thinner, shorter and smaller products. As the size of the semiconductor device is scaled down, the gate thickness becomes less and the spacer width becomes shorter, resulting in high gate-induced drain leakage (GIDL) and severe hot carrier effect.
In the conventional method, the implanting dosage of source/drain extension (SDE) regions is increased to resolve the said issues. However, the sheet resistance and gate-drain overlap capacitance are increased to affect the device performance. Therefore, how to effectively increase the spacer width to alleviate the GIDL and hot carrier effect has drawn high attention in the industry.